Agentic AI in Electronic Design Automation (EDA) Market

Market Overview

The Global Agentic AI in Electronic Design Automation (EDA) Market size is estimated at USD 1.70 Billion in 2026, and is projected to reach USD 30.46 Billion by 2035, exhibiting a CAGR of 37.8% during the forecast period.

Semiconductor design complexity at sub-3nm process nodes has outpaced human capacity for manual verification and physical closure. Agentic AI systems now operate across the full RTL-to-GDSII flow, not as assistants but as autonomous workflow executors replacing entire engineering task queues. ChipAgents' agentic verification tool, benchmarked on Google's OpenTitan project, delivered 80% less time on verification tasks versus conventional approaches, demonstrating that the performance gap between autonomous agents and human-directed flows has already widened to a commercially decisive level.

In February 2026, Cadence Design Systems officially launched the ChipStack AI Super Agent framework, targeting autonomous front-end SoC design and RTL code validation at scale. A single ChipStack internal benchmark autonomously processed 12,500 lines of RTL against a 62-page specification using over 200 LLM calls and approximately 10 million tokens, establishing the compute footprint that enterprise EDA pipelines now require at production scale.

Electronic Design Automation underpins every advanced semiconductor product, and the agentic AI layer now being embedded within it represents a structural shift in how chip companies convert design intent into manufacturable silicon. Semiconductor Manufacturing Equipment vendors and EDA platform providers are converging at the process-design interface, as agentic tools increasingly encode foundry-specific design-rule constraints directly into autonomous optimization loops.

Key Takeaways

• The market size is USD 1.70 Billion in 2026, and is projected to hit USD 30.46 Billion by 2035 at a CAGR of 37.8%.
• By Component: Agentic AI Software Platforms led as the largest category with a 70.5% share in 2026.
• By Agent Type: Verification Agents led with a 32.4% share in 2026.
• By Design Stage: Functional Verification led with a 34.6% share in 2026.
• By Deployment: Cloud-Based led as the largest and fastest-growing category with a 58.9% share in 2026.
• By Level of Autonomy: Semi-Autonomous Agents led with a 70.7% share in 2026.
• By Application: IC and SoC Design led with a 64.5% share in 2026.
• By End User: Fabless Semiconductor Companies led with a 37.5% share in 2026.
• By Region: North America led with a 48.9% share in 2026.
• Top key players include Cadence Design Systems, Synopsys, Siemens EDA, NVIDIA, and Microsoft.

Segment Analysis

Agentic AI Software Platforms accounted for 70.5% of component demand in 2026, the highest of any category.

Software platforms dominate because they serve as the orchestration layer across the entire EDA flow, abstracting tool heterogeneity and enabling agents to execute multi-step, multi-tool workflows autonomously. Cadence's Voltus InsightAI for power signoff illustrates the commercial value: the platform delivered approximately 2x productivity in EM-IR closure, fixed up to 95% of IR-drop violations before signoff, and improved IR closure time by 50%. Buyers purchasing platforms gain compounding returns as agent capability expands without requiring new tool procurement cycles.

AI Agents and Applications represent the fastest-scaling sub-layer within the component mix. Services revenue accelerates as implementation complexity rises with each agentic capability tier, pulling professional services engagements from deployment and tuning to ongoing model fine-tuning contracts. The shift favors vendors with pre-integrated platform-to-agent handoffs over point-tool providers relying on third-party agent wrappers.

Verification Agents led the Agent Type segment with a 32.4% share in 2026.

Verification represents the most compute-intensive and schedule-critical phase of semiconductor design, making it the natural entry point for agentic automation. ChipAgents achieved a 99.4% pass rate — 155 of 156 tasks — on NVIDIA's VerilogEval-Human benchmark, and ACE-RTL with Nemotron 3 Ultra reached a 97.1% average pass rate across nine CVDP task categories. These benchmark results have converted enterprise procurement teams from experimental pilots to full-scale deployment mandates. Agentic AI Orchestration within verification pipelines now coordinates multiple sub-agents across simulation, assertion checking, and coverage closure in parallel, compressing what were sequential multi-week workflows.

Design Agents and Debugging Agents occupy the next tier of commercial traction. Physical Design Agents and Optimization Agents address the layout and timing closure disciplines most severely impacted by the semiconductor talent shortage. Siemens Aprisa AI delivered a 10x productivity boost, 3x compute-time efficiency, 3x faster tapeout, and approximately 10% better PPA, setting a performance benchmark that pressures competing physical design tool vendors to accelerate their own agentic roadmaps.

With a 34.6% share in 2026, Functional Verification outpaced all other Design Stage categories.

Functional verification consumes the largest share of total chip design time and headcount, concentrating both the pain and the commercial incentive for agentic substitution. Cadence InnoStack AI Super Agent delivered approximately 2x acceleration of design turnaround times across implementation and signoff stages, confirming that productivity returns extend beyond standalone verification into the physical closure phases that follow it.

RTL Design and Generation represents the fastest-growing design stage by agent deployment velocity. LLM-driven hardware description language generation is shifting RTL authorship from manual coding to prompt-directed synthesis, pulling demand upward from verification into the generation phase itself. Physical Design, Logic Synthesis, and Signoff stages each attract specialist agent vendors targeting the sub-workflows within them, fragmenting what was previously a consolidated EDA vendor-controlled pipeline.

Cloud-Based deployment captured 58.9% of the Deployment segment in 2026, ahead of all rivals.

Cloud infrastructure removes the compute ceiling that bounded on-premises agentic workloads, enabling agents to run billions of compute hours and millions of concurrent simulation threads. Hyperscaler silicon programs at Google, Amazon, Microsoft, and Meta generate captive cloud-native demand. AI Accelerator Chip workloads running inside cloud EDA environments require agents capable of scaling GPU-accelerated simulation farms dynamically, which on-premises deployments cannot replicate without equivalent capital expenditure.

On-Premises deployment retains a base among defense and regulated semiconductor OEMs operating under export-control constraints that prevent design data from leaving controlled environments. Hybrid deployment grows as enterprises seek to run sensitive IP-bearing design stages on-premises while offloading compute-intensive verification bursts to cloud agents, requiring EDA platforms to support seamless context handoff across environments.

Semi-Autonomous Agents led the Level of Autonomy segment with a 70.7% share in 2026.

Semi-autonomous agents dominate because enterprise buyers require human-in-the-loop checkpoints for signoff decisions on high-value designs. An Infineon and RPTU multi-agent verification framework with human-in-the-loop refinement achieved a final average coverage of 97.73% and a 100% assertion pass rate across five open-source designs, validating the hybrid autonomy model as a commercially viable ceiling before full autonomy becomes trusted at production tapeout.

Fully Autonomous Agents represent the highest-growth autonomy tier. Early deployments at NVIDIA, AMD, and Google confirm that the technical capability for full autonomy exists at the agent level. AI-Assisted Agents serve customers earlier in the adoption curve who want performance gains without ceding design-decision authority, creating a natural upsell trajectory as comfort with agent outputs accumulates over time.

IC and SoC Design captured 64.5% of the Application segment in 2026, ahead of all rivals.

Every advanced AI processor, mobile SoC, and data-center accelerator produced in 2026 requires agentic verification and physical design support. Advanced Packaging and Chiplets represent the fastest-growing application sub-category, as multi-die architectures multiply the interface constraint variables that rule-based EDA toolchains cannot resolve at scale. PCB and System Design enters a new agentic growth phase as Cadence's AuraStack Super Agent scales autonomous workflows into system-level layout, crossing a threshold where PCB design automation becomes commercially comparable to IC flow automation.

Fabless Semiconductor Companies led the End User segment with a 37.5% share in 2026.

Fabless companies carry no foundry capital expenditure, concentrating their investment entirely in design productivity. Agentic EDA tools compress the headcount required per design cycle, extending the cost-competitiveness window for fabless players versus integrated device manufacturers. Hyperscalers and Custom Silicon Developers represent the fastest-growing end-user category, as in-house silicon programs at Google, Amazon, Microsoft, and Meta generate sustained, large-scale demand for autonomous EDA pipelines outside traditional vendor relationships.

Key Market Segments

By Component

• Agentic AI Software Platforms
• AI Agents and Applications
• Services

By Agent Type

• Verification Agents
• Design Agents
• Debugging Agents
• Physical Design Agents
• Optimization Agents
• Test and Validation Agents
• Multi-Agent Orchestration Systems

By Design Stage

• Functional Verification
• RTL Design and Generation
• Physical Design
• System and Architecture Design
• Logic Synthesis
• Testing and Debugging
• Signoff and Analysis

By Deployment

• Cloud-Based
• On-Premises
• Hybrid

By Level of Autonomy

• Semi-Autonomous Agents
• AI-Assisted Agents
• Fully Autonomous Agents

By Application

• IC and SoC Design
• Advanced Packaging and Chiplets
• PCB and System Design
• Analog and Mixed-Signal Design
• RF and Photonics Design

By End User

• Fabless Semiconductor Companies
• Integrated Device Manufacturers
• Hyperscalers and Custom Silicon Developers
• Foundries
• Automotive Semiconductor Companies
• Electronics OEMs
• Research Institutions

Regional Analysis

North America led the Agentic AI in EDA market with a 48.9% share in 2026, reflecting the concentration of hyperscaler silicon programs, fabless design houses, and the EDA vendor base within the United States.

North America

The United States hosts the headquarters and primary R&D operations of Cadence, Synopsys, and Siemens EDA's North American division, creating a home-market advantage where customers and vendors co-develop agentic capabilities in real production environments. Hyperscaler custom silicon programs at Google, Amazon, Microsoft, and Meta represent the largest single demand concentration for agentic EDA pipelines in any region. Semiconductor Packaging innovation concentrated in Arizona and Oregon fab corridors pulls chiplet-specific agentic design tools into production workflows ahead of any other geography.

Asia Pacific

Asia Pacific represents the fastest-growing region in the market, driven by TSMC's foundry dominance in Taiwan, Samsung's foundry expansion in South Korea, and China's state-directed semiconductor investment programs. TSMC's participation as a key player in agentic EDA reflects foundry-side demand for autonomous design-for-manufacturability optimization tools embedded directly into process design kit environments. Japanese and South Korean IDMs running advanced node programs generate incremental agentic EDA demand outside the fabless model that dominates North America.

Europe

Europe's agentic EDA demand concentrates in automotive semiconductor programs at Infineon, STMicroelectronics, NXP, and Bosch, where functional safety certification requirements impose verification burdens that multi-agent frameworks are uniquely positioned to address. The Infineon and RPTU research collaboration on formal verification multi-agent systems signals a Europe-specific adoption pathway through academic-industry partnerships before full commercial deployment.

Latin America

Latin America remains an early-stage market for agentic EDA, with demand primarily tied to electronics manufacturing services rather than original chip design. Brazil's semiconductor investment programs and Mexico's electronics OEM base represent medium-term demand vectors as regional design centers expand.

Middle East & Africa

Middle East governments are investing in sovereign semiconductor competency through research institution programs in the UAE and Saudi Arabia. Agentic EDA tools lower the talent barrier for new national design centers, making autonomous agent platforms a strategic enabler for semiconductor program formation in the region.

Key Regions and Countries

North America

• US
• Canada

Europe

• Germany
• France
• The UK
• Spain
• Italy
• Rest of Europe

Asia Pacific

• China
• Japan
• South Korea
• India
• Australia
• Rest of APAC

Latin America

• Brazil
• Mexico
• Rest of Latin America

Middle East & Africa

• GCC
• South Africa
• Rest of MEA

Macroeconomic Impact

Cross-industry enterprise AI deployment data from 2026 shows that the average organization ran 28 AI agents, with projections of 40 agents within 12 months — a 43% planned increase. Over 75% of surveyed organizations reported moderate-to-high value from AI automation projects, and only 2.5% reported failure or negative ROI. These cross-sector benchmarks normalize agentic AI investment for CFOs and CIOs at semiconductor companies evaluating EDA automation budgets, lowering the internal justification threshold for deployment.

Semiconductor capital expenditure cycles amplify EDA tool purchasing power when chip demand is strong and compress discretionary AI tooling budgets during inventory correction periods. Export control restrictions on advanced semiconductor technology, particularly between the United States and China, create a bifurcated agentic EDA market where foundry-specific model training data becomes a geopolitically managed resource rather than a freely shared commercial asset.

Market Dynamics

Driver: Sub-3nm Complexity Forces Autonomous Workflow Adoption

At sub-3nm process nodes, the verification search space exceeds what human-directed simulation teams can cover within competitive tape-out schedules. Synopsys' fully autonomous design verification agent delivered up to 50x faster time-to-validated RTL alongside a 20% additional coverage improvement, compressing weeks of verification into hours at DAC 2026. An Infineon and RPTU multi-agent verification framework achieved an initial formal coverage of 86.21%, rising to 97.73% with human-in-the-loop refinement, confirming that coverage quality scales with agent architecture maturity rather than raw compute alone.

Synopsys' autonomous debug-closure workflow demonstrated 25–40% reductions in debug cycle time in early evaluations conducted with AMD and Microsoft Discovery, saving many weeks of engineering effort per design cycle. In July 2026, Synopsys showcased its AgentEngineer technology at the Design Automation Conference, publicly validating long-running autonomous workflows with named industry partners and shifting market perception from experimental to production-grade. In April 2026, Cadence formalized its alliance with Google Cloud to natively optimize its autonomous portfolio using Gemini models, embedding cloud-native model acceleration directly into the EDA vendor stack.

Restraint: IP Confidentiality and Tool Lock-In Slow Agentic Layer Integration

Semiconductor IP confidentiality requirements and export control regulations severely restrict training data available for foundry-specific agentic model development, creating a capability ceiling where general-purpose agents underperform relative to foundry-tuned alternatives. Zero-shot agentic approaches achieved only approximately 69.85% average formal coverage versus nearly 98% for multi-agent frameworks with human-in-the-loop refinement, quantifying the performance penalty of deploying untrained agents into complex foundry-specific design environments.

Proprietary format lock-in across Cadence, Synopsys, and Siemens tool ecosystems creates integration friction for agentic AI layers attempting cross-tool orchestration. Tcl-command compatibility errors accounted for 31.7% of physical-design-stage failures for general-purpose agents before structured execution architectures reduced that figure to 0.0%, illustrating that tool interoperability is not a solved problem and demands purpose-built EDA-aware agent architectures rather than generic coding agents.

Opportunity: Analog, Mixed-Signal, and FPGA White Space Awaits Agentic Deployment

Analog and mixed-signal design automation remains near-zero for agentic AI penetration versus digital flow counterparts, representing the single largest underserved application segment relative to design complexity. Siemens EDA's self-verifying agentic characterization workflow reduced library characterization turnaround by roughly 10x, converting a weeks-long effort into days and an hours-long configuration setup into minutes, demonstrating that agentic gains are technically achievable in analog-adjacent workflows when purpose-built architectures are applied.

HORIZON, NVIDIA Research's self-evolving agent, reached a 100% pass rate on ChipBench, RTLLM-2.0, Verilog-Eval-v2, and nine CVDP task categories in 2026, starting from a first-iteration aggregate pass rate of 47.8%. FPGA prototyping workflows for defense and aerospace OEMs represent a parallel white-space opportunity, where strict design iteration timelines create willingness to pay for autonomous agent co-pilots that can compress multi-week iteration cycles to days without requiring full autonomy deployment.

Porter's Five Forces

Competitive rivalry within agentic EDA concentrates at the platform level between Cadence, Synopsys, and Siemens EDA, where proprietary tool ecosystems and existing customer relationships create structural advantages that new entrants cannot replicate quickly. Barriers to entry remain high because EDA-specific agent performance demands deep foundry PDK knowledge and tool-format fluency that general-purpose AI developers do not possess. Open-source agents scored under 25% on the harder ChipAgentsBench while UVM boilerplate agents reached only approximately 50% pass rates, demonstrating that commodity model providers cannot compete on performance without purpose-built EDA training. Buyer bargaining power is moderate because switching costs across integrated EDA flows are high, but the emergence of startup agentic platforms targeting RISC-V ecosystems introduces a credible alternative procurement path for cost-sensitive fabless buyers. Supplier power from LLM providers is rising as agent performance correlates strongly with foundation model quality. Different agent architectures built on the same foundation model showed RTL-to-GDS performance gaps of up to 86.27 points in benchmarked comparisons, and early HORIZON iterations on the hardest CVDP tasks started at 3.2% and 3.8% pass rates before self-evolving loops closed them to 100%, confirming that architecture and training methodology — not model access alone — determine competitive differentiation.

AI and Gen AI Impact

Reinforcement learning agents now operate in production tape-out environments at NVIDIA, Google DeepMind, and Synopsys, executing floorplanning, routing, and power grid optimization autonomously. Cadence's Verisium reinforcement-learning verification platform reduced regression cycles from approximately 24 hours to 3–5 hours in representative production cases, cutting the overnight batch simulation model that has defined chip verification scheduling for two decades. ACE-RTL agents lifted standalone model pass rates from 44.0%–68.6% to 94.3%–100.0% across three frontier models, confirming that agentic scaffolding multiplies base model capability beyond what raw model scaling alone achieves.

NVIDIA Nemotron 3 Ultra, a 550B-total / 55B-active-parameter MoE hybrid model with a 1M-token context window, delivered up to 5x higher throughput and 30% lower costs versus comparable open models for agentic RTL work. The HORIZON benchmark consumed 209.9 million total tokens per full evaluation run, of which approximately 91% were cached input tokens, establishing that token caching strategy is now a first-order cost management variable in large-scale agentic EDA deployments.

Market Trends

Super-Agent Architectures Absorb Point Tools Into Unified Autonomous Flows

Cadence AuraStack AI Super Agent cited up to 20x faster multiphysics performance and up to 15x faster design workflows at DAC 2026, benchmarks that redefine the performance floor buyers now expect from enterprise EDA platforms. LLM-driven hardware description language generation is shifting RTL authorship from manual coding to prompt-directed synthesis. Graph neural network architectures purpose-built for netlist optimization are moving from academic publication to commercial agent productization, pulling a new generation of optimization-specific agent vendors into the market ahead of the next major design node cycle.

Market Competition Overview

The agentic EDA market operates as a concentrated oligopoly at the platform layer, with Cadence, Synopsys, and Siemens EDA each deploying multi-agent super-agent architectures across the full chip design flow. Cadence's tool-level agents reduced multi-step engineering tasks from minutes to seconds by translating command sequences into natural-language interactions, illustrating the execution speed advantage that platform-native agents hold over third-party wrappers. Cadence's JEDAI orchestration layer operates with sub-20 millisecond overhead per LLM call, setting an infrastructure performance benchmark that constrains which orchestration architectures can operate without introducing pipeline bottlenecks at production scale.

Startup entrants — including ChipAgents, Agentrys, PrimisAI, Circuit Mind, Quilter AI, Celus GmbH, and Doide Computers — compete by targeting underserved sub-flows and open-ecosystem design environments. FluxEDA's structured execution architecture achieved an end-to-end RTL-to-GDS score of up to 97.94 and completed all three gated stages in 8 of 8 runs versus 3 of 8 for a general coding agent, demonstrating that architecture specificity generates a measurable competitive wedge against platform incumbents on defined sub-tasks.

Pricing Analysis

Token economics now function as a primary cost driver alongside traditional EDA license fees, creating a new pricing variable that customers and vendors must manage simultaneously. Siemens EDA reduced token costs by approximately 5x–10x via NeMo Switchyard and Nemotron models, with an additional 25% reduction from NeMo Gym optimization, demonstrating that model selection and inference architecture materially alter per-workflow operational cost structures. Nemotron 3 Ultra used 6,629 tokens per iteration on average — 28% fewer than GLM 5.2 at 9,156 tokens and 71% fewer than Kimi K2.6 at 22,579 tokens — showing that model efficiency differentials translate directly into per-design-cycle cost advantages.

Agent architecture quality creates extreme Token ROI divergence across providers. Two agents achieving identical design progress in an RTL-to-GDS benchmark differed by up to 141x in normalized Token ROI. A structured architecture run costing $0.56 scored 97.94 versus an unstructured run costing $0.11 that scored 13.33, establishing that lowest-cost-per-token procurement logic fails in agentic EDA where output quality and token efficiency are jointly determined by architecture, not price point alone.

Company Profiles

Cadence Design Systems operates the broadest agentic EDA portfolio in the market, spanning ChipStack (front-end RTL), InnoStack (implementation), AuraStack (PCB and packaging), and Verisium (verification) under a unified super-agent architecture. The ChipStack AI Super Agent delivered over 40x faster RTL validation cycles at NVIDIA, reducing a typical five-week verification loop to under one day. Thousands of NVIDIA engineers running billions of compute hours annually are deploying ChipStack agents to execute hundreds of dynamic simulations per engineer, establishing that the commercial deployment scale is no longer pilot-level. Cadence's current ChipStack deployments show approximately 2x productivity gains, with the platform architecture targeting up to 10x as agent capability and system maturity advance, tested against a PCIe 7.0 controller comprising approximately 1 million lines of RTL and a 6,000-page specification.

Synopsys competes through GPU-accelerated autonomous workflows deployed across more than 20 products in its 2026 portfolio. Synopsys delivered an 18x PrimeSim SPICE speedup and up to 3x productivity on Custom Compiler analog and mixed-signal layout synthesis, extending agentic performance claims into the analog domain where competitor coverage remains thinner. The strategic collaboration with Microsoft on the Discovery platform, alongside AMD's early evaluation participation, positions Synopsys as the primary agentic EDA partner for enterprise AI infrastructure developers building next-generation accelerator chips.

Key Players

• Cadence Design Systems
• Synopsys
• Siemens EDA
• NVIDIA
• Microsoft
• Google
• AMD
• TSMC
• Qualcomm
• Altera
• Tenstorrent
• Keysight Technologies
• Ansys
• Altium
• Zuken
• PrimisAI
• Circuit Mind Limited
• Quilter AI
• Celus GmbH
• Doide Computers

Supply Chain and Value Chain Analysis

The agentic EDA value chain flows from foundation model providers and cloud compute infrastructure through EDA platform vendors to semiconductor design houses, foundries, and end-system OEMs. Foundation model providers — including NVIDIA, Google, and Microsoft — now occupy a structurally upstream position in the EDA stack, as agent performance scales with model quality and inference infrastructure. EDA platform vendors capture the maximum value-add layer by converting foundation model capability into domain-specific autonomous workflows protected by proprietary tool integration, PDK knowledge, and benchmark-validated performance claims.

The biggest supply chain bottleneck sits at the foundry PDK interface, where agentic model training data is constrained by IP confidentiality agreements. Foundries control access to process-specific design rules, characterization libraries, and yield data that agentic optimization tools require to deliver PPA improvements beyond what generic training enables. Any EDA vendor or startup lacking direct foundry co-development agreements faces a performance ceiling against incumbents with embedded PDK-level access.

Regulatory Landscape

Export control regulations under the U.S. Export Administration Regulations and the Bureau of Industry and Security's entity list directly constrain agentic EDA deployment for Chinese foundries, fabless design houses, and research institutions by restricting access to advanced EDA tools and the foundation models trained on controlled process technology data. Compliance requirements create a bifurcated market where Chinese semiconductor programs must develop domestic agentic EDA capabilities in parallel with global vendors, sustaining domestic tool investment but reducing interoperability with leading-edge international design flows.

Functional safety standards — including ISO 26262 for automotive and DO-254 for aerospace — impose verification coverage requirements that agentic AI frameworks must formally demonstrate before regulators accept autonomous-agent-signed-off designs. Automotive semiconductor programs in Europe operate under these constraints, creating a certification pathway opportunity for vendors whose multi-agent verification frameworks can generate auditable coverage artifacts acceptable under functional safety review processes.

Investment and White Space Analysis

Venture investment in agentic EDA accelerated through 2026, with funding flowing directly into autonomous verification, root-cause analysis, and self-improving agent platforms. In July 2026, ChipAgents expanded its Series A funding to $134 million in a round led by B Capital to scale its automated root-cause analysis platform, signaling investor confidence in verification-focused agentic startups as a distinct fundable category. In August 2026, Agentrys raised $24.5 million to advance self-improving agent workforces targeting fabless semiconductor developers, with the company founded by former NVIDIA chip-AI researcher Mark Ren, demonstrating that pedigree-driven founding teams are attracting early institutional capital ahead of revenue scale.

White space concentrates in three domains: analog and mixed-signal design automation where agentic AI penetration remains near-zero, FPGA prototyping for defense and aerospace where iteration timeline pressure is acute, and RISC-V open-source chip ecosystems where startups can deploy agentic toolchains without inheriting the legacy licensing structures that constrain incumbent EDA vendors. Autonomous design-for-manufacturability optimization agents embedded directly into foundry PDK environments represent a high-value but capital-intensive entry point where foundry co-investment partnerships may be required to achieve competitive training data access.

Recent Developments

• August 2025: Semiconductor test and yield enhancement provider Semitronix, via SMTX Technologies Singapore, completed the acquisition of Belgian photonic integrated circuit design software firm Luceda Photonics, expanding its PIC design automation capabilities into the European photonics ecosystem.
• September 2025: Synopsys broadened its integration of the Ansys Engineering Copilot across its digital and analog toolsets, expanding generative and layout AI capabilities into existing customer workflows without requiring separate tool procurement.
• February 2026: Siemens EDA introduced its Questa One Agentic Toolkit, deploying domain-scoped Flow Agents to orchestrate complex IC design and verification closure across multi-step tool sequences.
• March 2026: Siemens EDA formalized its enterprise-scale orchestration strategy with the Fuse EDA AI System and Agent, designed to autonomously manage multi-tool semiconductor and 3D IC workflows at production scale.
• July 2026: Cadence Design Systems launched the AuraStack AI Super Agent via its Allegro AI Studio platform, scaling agentic workflows into system-level PCB and 3D packaging layout for the first time at commercial availability.

Report Scope